This application claims priority to Korean Patent Application No. 2002-39836, filed Jul. 9, 2002, which is herein incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a non-volatile memory device in which stored data is maintained without a power supply and a method of fabricating the same, and more particularly, to an electrically erasable programmable read-only memory (hereinafter, referred to as ‘EEPROM’) and a method of fabricating the same.
2. Description of the Related Art
Electrically erasable programmable non-volatile memory comes in different types, for example, EEPROM of a floating gate type, a metal-nitride-oxide-silicon (MNOS) type, a metal-oxide-nitride-oxide-silicon (MONOS) type, and a silicon-oxide-nitride-oxide-silicon (SONOS) type.
An example of a SONOS-type EEPROM is illustrated in FIGS. 1 and 2. FIGS. 1 and 2 are cross-sectional views of the SONOS-type EEPROM, shown along a bit line and a gate, respectively.
Referring to FIGS. 1 and 2, the SONOS-type EEPROM has a stacked structure comprising a lower oxide layer 20, a nitride layer 30, an upper oxide layer 40, and a polysilicon layer 50. The lower oxide layer 20 is a tunnel oxide layer, the nitride layer 30 is a memory (storage) layer, and the upper oxide layer 40 is a blocking layer for preventing the loss of a stored charge. The polysilicon layer 50 is a gate. The lower oxide layer 20, the nitride layer 30, the upper oxide layer 40, and the polysilicon layer 50 are sequentially formed on a substrate 10 in which isolation regions 15 are formed. Source/drain regions 60 are formed at both sides of the stacked structure in the substrate 10.
The SONOS-type EEPROM can be used in a compact semiconductor memory cell because it needs less voltage to program and erase than an EEPROM of the floating gate type. To achieve a more highly integrated SONOS-type EEPROM, the size of a memory cell needs to be reduced. As the size of the SONOS-type EEPROM is reduced, isolation of each memory cell becomes more important. Thus, an area for isolation of each cell needs to be secured. The size of the area of isolation limits the size of an active area in this case.
Therefore, a need exists for a memory cell having an enhanced active channel region without increasing the size of a planar unit cell, and a method for fabricating the same.